1. Field
Exemplary embodiments of the present invention relate to a signal output circuit and a semiconductor device.
2. Description of the Related Art
As mass society is developing rapidly, demands for various electronic equipments capable of high speed processing of high capacity data have been abruptly increased. As a measure for high speed processing of high capacity data in such electronic equipments, a semiconductor memory device is used. For example, a DDR (double data rate) semiconductor memory device is mainly used. Unlike the existing SDR (single data rate) semiconductor memory device, the DDR semiconductor memory device operates in synchronization with both the rising edge and the fall edge of a clock. In such a semiconductor memory device, a data output circuit including a driver for stably outputting data is used.
FIG. 1 is a configuration diagram of a conventional data output circuit.
Referring to FIG. 1, the data output circuit includes a pull-up transfer unit 110, a pull-down transfer unit 120, and an output driving unit 130.
Hereinafter, operations of the data output circuit will be described with reference to FIG. 1.
The pull-up transfer unit 110 is configured to transfer the data of a first line RDO to a pull-up line PUL during the activation period (e.g., high level period) of a rising clock RCLK and transfer the data of a second line FDO to the pull-up line PUL during the activation period (e.g., high level period) of a falling clock FCLK. The rising edge of the rising clock RCLK is synchronized with the rising edge of a system clock CLK which is used in a memory system, and the rising edge of the falling clock FCLK is synchronized with the falling edge of the system clock CLK. Accordingly, the rising clock RCLK and the falling clock FCLK are in an inverted relationship with respect to each other.
The pull-down transfer unit 120 is configured to transfer the data of the first line RDO to a pull-down line PDL during the activation period (e.g., high level period) of the rising clock RCLK and transfer the data of the second line FDO to the pull-down line PDL during the activation period (e.g., high level period) of the falling clock FCLK. The first line RDO is a line through which the data to be outputted in synchronization with the rising edge of the system clock CLK is transferred, and the second line FDO is a line through which the data to be outputted in synchronization with the falling edge of the system clock CLK is transferred (the data are transferred to the data output circuit through the lines RDO and FDO).
The output driving unit 130 is configured to pull-up drive an output node OUT in response to the signal of the pull-up line PUL or pull-down drive the output node OUT in response to the signal of the pull-down line PDL. The output driving unit 130 may include a PMOS transistor P having one end which is connected to the output node OUT, the other end to which a power supply voltage VDD is applied and a gate to which the signal of the pull-up line PUL is inputted and an NMOS transistor N having one end which is connected to the output node OUT, the other end to which a ground voltage VSS is applied and a gate to which the signal of the pull-down line PDL is inputted.
Hereinafter, entire operations of the data output circuit will be exemplarily described with reference to FIG. 1.
First, in the case where the high level data of the first line RDO is outputted during the activation period of the rising clock RCLK, since the data of the first line RDO is transferred to the pull-up line PUL and the pull-down line PDL by the pull-up transfer unit 110 and the pull-down transfer unit 120, respectively, the signals of the pull-up line PUL and the pull-down line PDL become high levels. Therefore, since the PMOS transistor P is turned off and the NMOS transistor N is turned on, the output node OUT is pull-down driven, and low level data acquired through inversion of the high level data of the first line RDO is outputted to the output node OUT.
Next, in the case where the low level data of the second line FDO is outputted during the activation period of the falling clock FCLK, since the data of the second line FDO is transferred to the pull-up line PUL and the pull-down line PDL by the pull-up transfer unit 110 and the pull-down transfer unit 120, respectively, the signals of the pull-up line PUL and the pull-down line PDL become low levels. Therefore, since the PMOS transistor P is turned on and the NMOS transistor N is turned off, the output node OUT is pull-up driven, and high level data acquired through inversion of the low level data of the second line FDO is outputted to the output node OUT.
The duty ratios between the high level periods and the low level periods of the rising clock RCLK and the falling clock FCLK, which are used to transfer the data of the first line RDO and the second line FDO to the pull-up line PUL and the pull-down line PDL, is near to 1:1. Hereinafter, it will be described with reference to FIG. 2 that data are transferred to the output driving unit 130 using the clocks RCLK and FCLK with duty ratios of 1:1.
FIG. 2 is a waveform diagram illustrating operations of the data output circuit shown in FIG. 1.
FIG. 2 shows the case where high level data is applied to the first line RDO and low level data is applied to the second line FDO such that the data of the first line RDO and the data of the second line FDO are alternately outputted by being inverted. In the high level period of the system clock CLK, the high level data of the first line RDO is outputted by being inverted, and in the low level period of the system clock CLK, the low level data of the second line FDO is outputted by being inverted.
Referring to FIG. 2, during the activation period of the rising clock RCLK, since the high level data of the first line RDO is transferred to the pull-up line PUL and the pull-down line PDL, the logic values of the signals of the pull-up line PUL and the pull-down line PDL become high. Accordingly, the PMOS transistor P is turned off and the NMOS transistor N is turned on, by which the output node OUT is pull-down driven (the low level data acquired through inversion of the high level data of the first line RDO is outputted). Further, during the activation period of the falling clock FCLK, since the low level data of the second line FDO is transferred to the pull-up line PUL and the pull-down line PDL, the logic values of the signals of the pull-up line PUL and the pull-down line PDL become low. Accordingly, the PMOS transistor P is turned on and the NMOS transistor N is turned off, by which the output node OUT is pull-up driven (the high level data acquired through inversion of the low level data of the second line FDO is outputted).
In this regard, because the duty ratios of the rising clock RCLK and the falling clock FCLK are 1:1, the waveforms of the signal of the pull-up line PUL and the signal of the pull-down line PDL are substantially the same as shown in FIG. 2. Thus, the rising edges and the falling edges of the signals of the pull-up line PUL and the pull-down line PDL overlap with each other. Due to this fact, the PMOS transistor P and the NMOS transistor N are likely to be simultaneously turned on. If the PMOS transistor P and the NMOS transistor N are simultaneously turned on, short current may flow between a power supply voltage terminal 101 and a ground voltage terminal 102 and power consumption of the data output circuit may increase.